1. Field of the Invention
The present invention relates to a semiconductor device housing a test circuit that determines whether or not an interface circuit, which transmits or receives data to or from an external memory, normally operates, and especially relates to a semiconductor device including a DDRif (double data rate interface circuit) that transfers data in synchronism with the rise or fall of a clock signal so as to transmit or receive data at high speed.
2. Description of the Background Art
A DDRif in the prior art has been configured by: a DLL (delay locked loop circuit) that determines a phase shift amount; a phase shifter that shifts a DQ (data signal) at 90 degrees at write time; a phase shifter that shifts a DQS (data strobe signal) at 90 degrees at read time; a circuit that detects a preamble period at read time; a FIFO that resyncronizes data at read time to a clock; and a buffer capable of inputting or outputting data, and outputting a clock/command (see ITC 2004 Digest of Technical Paper, “AC IO Loopback Design for High Speed uProcessor IO Test”, B Provost, et al.).
Whether or not the DDRif with the above-mentioned configuration normally operates has been determined by measurement of a variety of AC  timings using an external tester. For example, a characteristic fluctuation has been determined using a highly accurate tester at the time of evaluation, and a characteristic evaluation has been performed using an alternative simple tester in a test before shipment.
Further, Japanese Patent Application Laid-Open No. Hei 11-72540 shows a semiconductor device including a circuit in which an input clock is shifted in accordance with instruction data from the outside and then taken in, and a delay amount is measured from a result of comparison with the taken-in data, to measure input setup/hold time.
However, a DDR-SDRAM with an enhanced speed has been required to operate with a higher degree of accuracy, and in order to ensure a variety of AC timings defined with respect to the DDR-SDRAM by using an external tester, a highly accurate tester capable of performing a very high-speed operation is needed, thereby causing a problem of increased test cost. Further, in the case of determining accuracy of an internal operation by using an external tester, there has been a problem in that under the influence of a channel along which data is pulled out to the external tester, a highly accurate test cannot be performed.
Further, in the configuration shown in Japanese Patent Laid-Open No. Hei 11-72540, it is necessary in generating a desired phase difference to read a DLL code in a locked state to the outside, calculate in the outside a delay amount per unit bit from the read code, and again set in a register a code shifted by a desired phase difference based upon the calculation result. Although the DLL is a circuit in which stable timings are generated even  with variations in condition on a chip, there has been a problem in that a value of a register cannot be changed when register setting is made and hence the DLL cannot follow variations in condition during a test, which may result in a phase amount away from a desired test point.
An object of the present invention is to obtain a semiconductor device that houses a test circuit capable of following a predetermined phase during a test to determine inexpensively whether or not a DDRif normally operates.
A semiconductor device of the present invention is a semiconductor device which transmits or receives a signal to or from an external memory by a DDR system, including a DLL circuit, an arithmetic circuit, first to forth registers, and a transmission circuit.
The DLL circuit determines a phase shift amount.
The arithmetic circuit is connected to the DLL circuit and shifts the phase shift amount by a predetermined phase based upon a test mode signal at test mode time.
The first to fourth registers are connected to the arithmetic circuit and set the phase shift amount shifted by the predetermined phase.
The transmission circuit is connected to the first to fourth registers and a first terminal and a second terminal that transmit or receive a signal to or from the external memory, and shifts a phase based upon the phase shift amount set in the first to fourth registers to transmit or receive a signal.
The transmission circuit has a first phase shifter, a first bidirectional buffer, a second phase shifter, a third phase shifter, a second bidirectional buffer, a fourth phase shifter, and a FIFO. 
The first phase shifter is connected to the first register and phase-shifts a first signal to be outputted to the first terminal based upon the phase shift amount set in the first register.
The first bidirectional buffer is connected to the first phase shifter and the first terminal, and outputs or inputs the first signal or a second signal to or from the external memory, or loops back the first signal at the test mode time.
The second phase shifter is connected to the first bidirectional buffer and phase-shifts the first signal or the second signal based upon the phase shift amount set in the second register.
The third phase shifter is connected to the third register and phase-shifts a third signal to be outputted to the second terminal based upon the phase shift amount set in the third register.
The second bidirectional buffer is connected to the third phase shifter and the second terminal, and outputs or inputs the third signal or a fourth signal to or from the external memory, or loops back the third signal at the test mode time.
The fourth phase shifter is connected to the second bidirectional buffer and the fourth register, and phase-shifts the third signal or the fourth signal based upon the phase shift amount set in the fourth register.
The FIFO is connected to the second and fourth phase shifters, and takes out the first or second signal correspondingly to the third or fourth signal.
According to the present invention, an arithmetic circuit is provided at the latter step of a DLL to set registration such that a phase shift amount  sequentially changes from the pass side to the fail side so that setup/hold time can be measured without the use of an external tester capable of high-speed operation with high accuracy. Further, a test circuit is housed, thereby to allow reduction in test cost.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.